The development of complicated integrated circuits often requires powerful numerical simulation programs. For example, circuit simulation is an essential part in the design flow of integrated circuits, helping circuit designers to verify the functionality and performance of their designs without going through expensive fabrication processes. Examples of electronic circuit simulators include the Simulation Program with Integrated Circuit Emphasis (SPICE) developed at the University of California, Berkeley (UC Berkeley), and various enhanced versions or derivatives of SPICE, such as SPECTRE, developed by Cadence Design Systems, Inc. SPICE and its derivatives or enhanced versions will be referred to hereafter as SPICE circuit simulators, or SPICE.
An integrated circuit is a network of circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET), metal-oxide-semiconductor field effect transistors (MOSFET), metal-semiconductor field effect transistors (MESFET), thin-film transistors (TFT), etc. SPICE models a circuit in a node/element fashion, i.e., the circuit is regarded as a collection of various circuit elements connected at nodes. At the heart of SPICE is the so-called Nodal Analysis, which is accomplished by formulating nodal equations (or circuit equations) in matrix format to represent the circuit and by solving these nodal equations. The circuit elements are modeled by device models, which produce model results that are represented in the circuit equations as matrices.
A device model for modeling a circuit element, such as the SPICE model for modeling MOSFET devices, developed by UC Berkeley, typically includes model equations and a set of model parameters that mathematically represent characteristics of the circuit element under various bias conditions. For example, a circuit element with n terminals can be modeled by the following current-voltage relations:Ii=fi(V1, . . . , Vn,t) for i=1, . . . , n,where Ii represents the current entering terminal I; Vj(j=1, . . . , n) represents the voltage or terminal bias across terminal j and a reference terminal, such as the ground; and t represents the time. The Kirchhoff's Current Law implies that the current entering terminal n is given by
      I    n    =            ∑              i        =        1                    n        -        1              ⁢                  ⁢                  I        i            .      A conductance matrix of the circuit element is defined by:
      G    ⁡          (                        V          1                ,        …        ⁢                                  ,                  V          n                ,        t            )        :=            (                                                                  ∂                                  f                  1                                                            ∂                                  V                  1                                                                          …                                                              ∂                                  f                  1                                                            ∂                                  V                  n                                                                                          ⋮                                ⋱                                ⋮                                                                              ∂                                  f                  n                                                            ∂                                  V                  1                                                                          …                                                              ∂                                  f                  n                                                            ∂                                  V                  n                                                                        )        .  To model the circuit element under alternating current (AC) operations, the device model also considers the relationship between node charges and the terminal biases:Qi=qi(V1, . . . , Vn,t) for i=1, . . . , n.where Qi represents the node charge at terminal i. Thus, the capacitance matrix of the n-terminal circuit element is defined by
      C    ⁡          (                        V          1                ,        …        ⁢                                  ,                  V          n                ,        t            )        :=            (                                                                  ∂                                  q                  1                                                            ∂                                  V                  1                                                                          …                                                              ∂                                  q                  1                                                            ∂                                  V                  n                                                                                          ⋮                                ⋱                                ⋮                                                                              ∂                                  q                  n                                                            ∂                                  V                  1                                                                          …                                                              ∂                                  q                  n                                                            ∂                                  V                  n                                                                        )        .  
A complex integrated circuit may contain millions of circuit elements such as transistors, resistors, and capacitors. The design and simulation of such a complex integrated circuit may involve multiple teams of engineers. It is advantageous to partition the design of such complex integrated circuit using a hierarchical approach, whereby certain circuit elements are grouped together and may be reused repeatedly through the integrated circuit or in a subsequent design. A method and system for design and simulation of an integrated circuit with a hierarchical data structure are disclosed by U.S. patent application Ser. No. 10/724,277, entitled “System and Method for Simulating a Circuit Having Hierarchical Structure,” which, filed on Nov. 26, 2003, and commonly owned by Cadence Design Systems, Inc., is incorporated expressly by reference in its entirety herein.
As the number of circuit components of a System-on-Chip (SoC) integrated circuit continues to increase, the convention SPICE simulation fails to meet the simulation demand of such SoC integrated circuit due to speed and capacity limitations. One problem is that the SPICE simulation has become a time-consuming process for many practical applications. Another problem is that the SPICE simulation may run out of computer memory before completion of the simulation, which leads to waste of valuable resources and time.
A Fast SPICE circuit simulator attempts to improve the speed and memory usage of the SPICE circuit simulator while maintaining accuracy of the simulation. One example of a commercial Fast SPICE circuit simulator is the Virtuoso Ultrasim Fast SPICE circuit simulator developed by Cadence Design Systems, Inc. One improvement of the Fast SPICE circuit simulator over the conventional SPICE circuit simulator is the ability to identify and simulate the multi-rate characteristics of a large integrated circuit. It is well known that many large integrated circuits may demonstrate the multi-rate characteristics. That is, at a particular point in time, some portions of the circuit may have high rate of activities, while other portions may not have any activities at all. For example, when one portion of a direct random access memory (DRAM) is being accessed, other portions of the DRAM are typically in idle state. The computational cost of inactive portions may be reduced significantly by using circuit partitioning and multi-rate simulation.
Thus, using a Fast-SPICE simulator along with circuit partitioning techniques would address some of the issues of the conventional SPICE simulator. In a conventional circuit partitioning technique, an integrated circuit is divided into a set of regions formed by directly-coupled or channel-connected elements. A partition usually consists of some transistors topologically connected together through their sources or drains. Examples of circuit partition techniques are described in “Mixed-mode Simulation and Analog Multilevel Simulation,” by Saleh, Resve A., Kluwer Academic Publishers, 1994, pp. 93. A Fast-SPICE simulation of a partition is triggered only when there is an event at its input, for example, when the voltage at the input node changes more than a predefined threshold.
However, the traditional partitioning techniques based on channel connection partitioning are insufficient for addressing complex direct-coupling, indirect-coupling, or non-topological-coupling effects of sub-micron integrated circuit designs. Therefore, there is a need for a new method and system for partitioning sub-micron integrated circuits for Fast SPICE simulation.